The present invention relates to transistors and their fabrication. More specifically, the invention relates to bipolar transistors.
Cutoff frequency (fT) and maximum oscillation frequency (fmax) are the most representative measures of high-speed transistors performance. Hence, the design and optimization efforts for high-speed transistors are mostly directed toward maximizing these two parameters. Fmax is a function of fT and of parasitic resistances and parasitic capacitances (collectively referred to herein as “parasitics”) between elements of the transistor according to the formula fmax=(fT/8π*Ccb*Rb)1/2. As indicated by the equation, one of the device parameters that influence fT and fmax is the base to collector capacitance (Ccb). Ccb is a parasitic capacitance whose value is a consequence of the particular structure and method used to fabricate the transistor. Its value has a limiting effect on the value of fmax.
FIG. 1 is a diagram illustrating the structure of a prior art bipolar transistor 10. As illustrated therein, Ccb is made up of several capacitance components in parallel, including the intrinsic capacitance Ccb(intrinsic) 12 between the base and collector in the intrinsic region, and the parasitic capacitance Ccb(extrinsic) 15, which includes Ccb(extrinsic base) 14 between the extrinsic base and the collector, and the capacitance Ccb(STI) 16 across the shallow trench isolation (STI). More than two-thirds of total Ccb comes from the extrinsic parasitic portion Ccb(extrinsic). This parasitic capacitance results from the overlap between the collector and base regions outside the active intrinsic transistor region that is located under the emitter. The overlap area between these regions cannot be easily minimized by lithography, due to limitations imposed by overlay and alignment tolerances. The value of this parasitic capacitance is a function of the concentration of dopants at the junction between the collector and base regions. A high concentration of dopants results in the junction between the two regions having a narrow depletion region width. In such case, a relatively high capacitance results, as understood from the equation for the capacitance of a C=kA/d, where C is the value of the capacitance, A is the overlap area between the base and the collector, and the distance d is the width of the depletion region at the junction. The depletion width of the junction between collector and the base region is subject to being decreased during fabrication by transport enhanced diffusion of dopants from the base region to the collector region, which further increases the parasitic capacitance.
In view of the foregoing, it would be desirable to provide a bipolar transistor structure and method of fabricating a bipolar transistor in which the junction depletion region width between the collector region and the extrinsic portion of the base region is increased, to reduce the parasitic extrinsic component of Ccb without adversely affecting other device parameters.